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Altium''s unified design eliminates barriers FPGA to PCB

by: Dec 10,2013 1241 Views 0 Comments Posted in Engineering Technical

PCB design PCB wiring plate PCB wiring PCB layout

Altium Altium company announced the latest integrated electronic product development system Altium Designer 6.0 greatly enhanced the FPGA - PCB "> PCB ability of collaborative design, the engineer can make full use of FPGA as the platform system, and simplify the large-scale FPGA and physical PCB" > PCB platform integration. Although it has long been recognized benefits of FPGA to logic development, but these devices are integrated into the PCB with the challenge of the design process, will make the PCB circuit board design become very complex and leads to the overall design time long. Usually without considering the FPGA pin assignment in PCB layout that is, in the dense packaging technology used in the large-scale programmable devices will make the PCB wiring become a great challenge.

Altium Designer broke the use of FPGA, connect the hard and soft PCB platform and software to connect the logic of the development together, which is composed of embedded intelligent by programming on the PCB circuit board to create a full application . Altium Designer 6.0 levels improved the FPGA design and PCB design, the integration between the development of a lot of new features, combined with large-scale programmable devices now, they to streamline the product development.

"Large availability of FPGA devices are changing the engineers in the system design method, the product can add more intelligent and shorten the design time, at the same time reduce the manufacturing cost." Altium's founder and CEO Nick Martin said, "Altium Designer 6.0 can help engineers in embedded intelligence and physical design make full use of FPGA to provide benefits, the unity of the system characteristic broke in mainstream widely adopted in the design of the programmable device of the obstacles, so that we can make full use of these devices extension resources, simplify the logical and physical design."

Altium Designer 6.0 introduced the concept of dynamic network redistribution, PCB wiring can be online during the exchange of the FPGA pin. This includes the redistribution in advance wiring subnet and difference signal to exchange links, difference signal to an LVDS resources available on the FPGA device fully. Dynamic network redistribution at board level has strengthened the FPGA pin optimization engine that allows engineers to take full advantage of the FPGA device pin can be reprogrammed features, in PCB wiring plate to obtain the optimal solution. Altium Designer system allows the unity on exchange of pin and the FPGA board level to complete the project of automatic synchronization, reduce manually adjust the time consuming of I/O processing.

Usually the FPGA device with a large number of pin type is intensive BGA encapsulation. It brings to the prototype stage of debugging difficult, because the pin cannot directly detect device. Altium Designer LiveDesign development approach allows engineers in development can interact directly with design based on FPGA. Altium Designer 6.0 has improved the JTAG device browser, can provide all the JTAG device in the system, according to the state of pin during the commissioning engineers can real-time detect pin signal state. Pin status can also be in the source schematic and PCB layout, according to the dynamic 'positioning' view the signal status in the design documents. Other Altium Designer of virtual instrument, the FPGA is used to set and monitor the signal inside the FPGA, give designers provide a full state diagram of the circuit operation, for logical and physical commissioning of the system.

The FPGA system online test in Altium Designer is improved in 6.0, provide enhanced logic analyzer (LAX) virtual instrument. Configurable LAX can monitor the FPGA from 8 bits to 64 bits within the bandwidth of the bus, support for multiple connection signal set. Arbitrary signal can be used to trigger the input or selected as the data source. When LAX can be configured to connect to the processor instruction bus, the bus data can be displayed as the disassembly code instructions, code related problems can be easily in the virtual instrument output tracking.

Altium Designer 6.0 32-bit processor system based on FPGA is also have more generality, support a large number of third-party processor, the soft core and division of including Xilinx ® MicroBlaze soft processor ™, Sharp ® BlueStreak ™ LH79520 (based on ARM720T) and AMCC ® PowerPC ® 405 cr discrete processors. Support these new devices, to have the 32-bit targets and eight independent soft processor support Altium Designer design system, make the designers when using FPGA for embedded system development more flexible. Altium Designer 6.0 provides package connector kernel can help designers to locate support third-party processor, while retaining the Altium Designer environment all the design features, including the use of Altium Designer conveniently connect virtual instrument based on FPGA with LiveDesign peripherals and debug. Altium based on 9 compiler tool chain to ensure that all the software compatibility between processors, parcel connectors provide hardware compatibility kernel. This means that the embedded designer without costly redesign engineering cost between processor design.

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